1. Field of the Invention
The present invention relates to a dynamic random access memory structure and a manufacturing method thereof. More particularly, the present invention relates to a dynamic random access memory structure having a vertical transistor and a deep trench capacitor and a manufacturing method thereof.
2. Description of Related Art
In the semiconductor industry, the dynamic random access memory (DRAM) is an important integrated circuit under constant studies and development. A DRAM cell generally includes a transistor and a capacitor controlled by the transistor. Presently, a structure of deep trench capacitor is developed in the DRAM industry, by which a capacitor is fabricated in the substrate to reduce the use of substrate area. Generally, the transistor of the DRAM having a deep trench capacitor is located horizontally on the substrate surface.
With the development of technology, miniaturization of the components is required, and the length of the channel region of a DRAM transistor is gradually shortened for improving the operation speed of the component. However, this will cause a serious short channel effect and a reduction of the on current of the transistor. A conventional solution for resolving the above problems is to increase the doping concentration of the channel region. However, this method may also increase the leakage, and therefore reduce the reliability of components. Moreover, a conventional DRAM has a narrow process window, misalignment usually occurs due to an overlay error between the deep trench and the gate.
To solve the problems of the conventional techniques, a structure of vertical transistor is provided in the DRAM industry for substituting the horizontal transistor, by which a vertical transistor is fabricated in a deep trench and disposed above a deep trench capacitor, and the vertical transistor is electrically connected to the deep trench capacitor through a buried strap (BS) formed on the sidewalls of the deep trench. However, the doping concentration of the buried strap is generally increased to ensure the buried strap electrically connecting the vertical transistor, and this will cause a floating body effect due to abnormal contact between the buried strap and the adjacent deep trench. The floating body effect means that the charges cannot discharge through the silicon substrate due to insulation of the buried strap. This problem may reduce the reliability and stability of the components.